1. Field of the Invention
The present invention relates to a technique for realizing power saving in a data processing apparatus.
2. Description of the Related Art
Heretofore, LSIs used in data processing have been focused on more for their processing speed and other capabilities rather than their power consumption. However, in recent years, following increases in the speed and integration density of LSIs, the importance of techniques for reducing power consumption has been increasing, in order to suppress the power consumption of the overall chip.
One way of realizing reduced power consumption in LSIs that has been proposed involves stopping the supply of the clock signal during periods in which processing modules do not need to be operated. For example, a circuit disclosed in Japanese Patent Laid-Open No. 08-054954 (Document 1) detects the input of data to a processing circuit, and supplies a clock signal for a preset period that is long enough for the processing circuit to process the input data. Unnecessary power consumption is then reduced in periods other than when processing is performed by lowering the clock frequency.
However, with the technology set forth in the abovementioned Document 1, there is a problem in that although the supply of a clock signal can be performed for a stipulated period with respect to input data of a predetermined data length, processing cannot be flexibly performed on input data of a variable length.